LAYOUT METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

• Main Authors: OGATA KATSUYA, HIRAMOTO TAKANORI, HINO TOSHIO, SAKATA TAKESHI, MIZUNO YUTAKA
• Format: Patent
• Language: English
• Published: 10.01.2013
• Subjects: APPARATUS SPECIALLY ADAPTED THEREFOR; BASIC ELECTRIC ELEMENTS; CINEMATOGRAPHY; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; ELECTROGRAPHY; HOLOGRAPHY; MATERIALS THEREFOR; ORIGINALS THEREFOR; PHOTOGRAPHY; PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES; PHYSICS; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To suppress variation in characteristics of a transistor which is caused by double patterning.SOLUTION: A plurality of gate electrode patterns 10-15 arranged in parallel to each other are set to be a first pattern which is formed in a first exposure step of a double patterning...