LAYOUT METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To suppress variation in characteristics of a transistor which is caused by double patterning.SOLUTION: A plurality of gate electrode patterns 10-15 arranged in parallel to each other are set to be a first pattern which is formed in a first exposure step of a double patterning...

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Bibliographic Details
Main Authors OGATA KATSUYA, HIRAMOTO TAKANORI, HINO TOSHIO, SAKATA TAKESHI, MIZUNO YUTAKA
Format Patent
LanguageEnglish
Published 10.01.2013
Subjects
APPARATUS SPECIALLY ADAPTED THEREFOR
BASIC ELECTRIC ELEMENTS
CINEMATOGRAPHY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
ELECTROGRAPHY
HOLOGRAPHY
MATERIALS THEREFOR
ORIGINALS THEREFOR
PHOTOGRAPHY
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:PROBLEM TO BE SOLVED: To suppress variation in characteristics of a transistor which is caused by double patterning.SOLUTION: A plurality of gate electrode patterns 10-15 arranged in parallel to each other are set to be a first pattern which is formed in a first exposure step of a double patterning and to be a second pattern formed in a second exposure step, alternately (step S1). A circuit containing a transistor pair in which the first pattern and the second pattern are connected in parallel to each other is laid out (step S2), thereby variation in characteristics of a transistor caused by the double patterning is suppressed.
Bibliography:Application Number: JP20110142067