SYSTEM TO MAINTAIN LOW-COST CACHE COHERENCY FOR ACCELERATORS

PROBLEM TO BE SOLVED: To reduce consumption of inter-node bandwidth by communications maintaining coherence between accelerators and CPUs.SOLUTION: CPUs 210 and accelerators 220 may be clustered on separate nodes in a multiprocessing environment. Each node 0, 1 that contains a shared memory device 2...

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Bibliographic Details
Main Authors CLARK SCOTT DOUGLAS, WOTTRENG ANDREW HENRY
Format Patent
LanguageEnglish
Published 20.09.2012
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PROBLEM TO BE SOLVED: To reduce consumption of inter-node bandwidth by communications maintaining coherence between accelerators and CPUs.SOLUTION: CPUs 210 and accelerators 220 may be clustered on separate nodes in a multiprocessing environment. Each node 0, 1 that contains a shared memory device 212, 222 may maintain a directory to track blocks of shared memory that may have been cached at other nodes. Therefore, command and addresses may be transmitted to processors and accelerators at other nodes only if a memory location has been cached outside of a node. Additionally, because accelerators generally do not access the same data as CPUs, only initial read, write, and synchronization operations may be transmitted to other nodes. Intermediate accesses to data may be performed non-coherently. As a result, inter-chip bandwidth consumed for maintaining coherence may be reduced.
Bibliography:Application Number: JP20120106285