INSULATED GATE TYPE SEMICONDUCTOR DEVICE

• Main Authors: YAGI HARUYOSHI, YAJIMA MANABU
• Format: Patent
• Language: English
• Published: 10.09.2012
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To solve the problem that a lead-out part of a gate lead-out wiring for leading a gate electrode of a MOSFET out in the periphery of a substrate constitutes an inactive region where transistor cells C of the MOSFET functioning with equal efficiency as in an element region cannot be disposed, which means that, if the gate lead-out wiring is laid along four sides of a chip, the inactive region increases and limitations are imposed on area expansion of the element region or contraction of a chip area.SOLUTION: Gate lead-out wirings and conductors which connect the gate lead-out wirings and protective diodes are laid in the form of a straight line not bent along the same side of the chip. Also, bent portions of a first gate electrode layer extending on top of these and connecting these and the protective diodes are limited to one spot or less. Furthermore, the protective diodes are disposed adjacent to the conductors or the gate lead-out wirings and some of the protective diodes are disposed in close proximity to a gate pad section.