TIMING ADJUSTMENT CIRCUIT FOR MEMORY INTERFACE AND METHOD

• Main Authors: TSUCHIYA SHIGEHIRO, OTA TETSUSHI, YAMAHARA YOSUKE, KITO HIDEAKI, IIJIMA HIROAKI
• Format: Patent
• Language: English
• Published: 09.08.2012
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

PROBLEM TO BE SOLVED: To provide a timing adjustment circuit for a memory interface in which gate timing can be adjusted in accordance with a phase of an inputted data strobe signal, and a method.SOLUTION: In a timing adjustment circuit, a sampling unit 11 samples a data strobe signal DQS predetermi...