TIMING ADJUSTMENT CIRCUIT FOR MEMORY INTERFACE AND METHOD

• Main Authors: TSUCHIYA SHIGEHIRO, OTA TETSUSHI, YAMAHARA YOSUKE, KITO HIDEAKI, IIJIMA HIROAKI
• Format: Patent
• Language: English
• Published: 09.08.2012
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

PROBLEM TO BE SOLVED: To provide a timing adjustment circuit for a memory interface in which gate timing can be adjusted in accordance with a phase of an inputted data strobe signal, and a method.SOLUTION: In a timing adjustment circuit, a sampling unit 11 samples a data strobe signal DQS predetermined number of times in accordance with a phase controlled sampling clock, an initial value setting unit 12 sets an initial value for a phase shift amount of a source gate signal from a result of sampling during which a pull-down circuit 2 is operating, and a correction unit 13 determines a correction direction of the set phase shift amount from a result of sampling during which the pull-down circuit 2 is not operating. In accordance with the phase shift amount determined by a phase shift amount determination unit 14 on the basis of output from the initial value setting unit 12 or the correction unit 13, a delay unit 15 delays the source gate signal and outputs a gate signal for gating the data strobe signal DQS.