MANUFACTURING METHOD OF SINGLE CRYSTAL SEMICONDUCTOR WAFER

PROBLEM TO BE SOLVED: To provide a semiconductor wafer that does not cause any problem when further size miniaturization is performed.SOLUTION: A single crystal semiconductor wafer has a region where defects are reduced. The region where the defects are reduced has density of GOI related defects in...

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Bibliographic Details
Main Authors FRIEDRICH PASSEK, HUBER ANDREAS, KNERER DIETER, LAMBERT ULRICH
Format Patent
LanguageEnglish
Published 12.07.2012
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS
SEMICONDUCTOR DEVICES
TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
TECHNICAL SUBJECTS COVERED BY FORMER USPC
TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Summary:PROBLEM TO BE SOLVED: To provide a semiconductor wafer that does not cause any problem when further size miniaturization is performed.SOLUTION: A single crystal semiconductor wafer has a region where defects are reduced. The region where the defects are reduced has density of GOI related defects in a range of 0-0.1 piece/cm. As a whole, the region accounts for unit area ratio of 10-100% of a planar flat surface of the semiconductor wafer. In that case, a remaining region of the semiconductor wafer has a clearly higher defect density than the region where the defects are reduced.
Bibliography:Application Number: JP20120023770