COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) STRUCTURE

PROBLEM TO BE SOLVED: To provide a complementary metal oxide semiconductor integration process that allows a plurality of silicide metal gates to be prepared on a gate dielectric.SOLUTION: There is provided a CMOS silicide metal gate integration method capable of eliminating a demerit of generation...

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Main Authors JAKUB T KEDZIERSKI, SERENDRA MAHESWARAN, RICKY S AMOS, MOCUTA ANDA C, NARAYANAN VIJAY, BOYD DIANE C, CYRIL CABRAL JR, LI YING, RICHARD D KAPLAN, ANNE L ZEUGEN, VICTOR KU, LEE WOO-HYEONG
Format Patent
LanguageEnglish
Published 15.03.2012
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PROBLEM TO BE SOLVED: To provide a complementary metal oxide semiconductor integration process that allows a plurality of silicide metal gates to be prepared on a gate dielectric.SOLUTION: There is provided a CMOS silicide metal gate integration method capable of eliminating a demerit of generation of variations in the height of poly Si gate stock which varies a silicide metal gate phase. The integration method minimizes the complexity of the process, thereby restraining the manufacturing cost of a CMOS transistor from increasing.
Bibliography:Application Number: JP20110187435