DATA PROCESSOR
PROBLEM TO BE SOLVED: To accelerate data processing rather than a system for starting circuits which can be simultaneously reconstituted by reconstituting them in a lump on a reconfigurable circuit. SOLUTION: A reconstitution control circuit 200 reconstitutes blocks A, B, C (they constitute pipeline...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
22.09.2011
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Subjects | |
Online Access | Get full text |
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Summary: | PROBLEM TO BE SOLVED: To accelerate data processing rather than a system for starting circuits which can be simultaneously reconstituted by reconstituting them in a lump on a reconfigurable circuit. SOLUTION: A reconstitution control circuit 200 reconstitutes blocks A, B, C (they constitute pipelines in this order) simultaneously reconstituted on an FPGA 100 in a conventional case one by one in order from the head block A. When the block A is reconstituted, the execution of the data processing is started, and the block B is reconstituted in parallel with the data processing. When the block B is reconstituted, the execution of the data processing is started, and the block C is reconstituted in parallel with the data processing. After the reconstitution of the block C is completed, the block A, B, C simultaneously operate to execute pipeline processing. COPYRIGHT: (C)2011,JPO&INPIT |
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Bibliography: | Application Number: JP20100054133 |