SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide an SRAM cell with small dimensions, capable of performing writing by using differential motion without having an effect of a path of write on a state held upon read.SOLUTION: The SRAM cell has NMOS drive transistors MDB and MDT and PMOS load transistors MLB and MLT a...

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Bibliographic Details
Main Authors YAMAOKA MASANAO, SAKATA TAKESHI
Format Patent
LanguageEnglish
Published 20.01.2011
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PROBLEM TO BE SOLVED: To provide an SRAM cell with small dimensions, capable of performing writing by using differential motion without having an effect of a path of write on a state held upon read.SOLUTION: The SRAM cell has NMOS drive transistors MDB and MDT and PMOS load transistors MLB and MLT as with a conventional 6 transistor SRAM cell, configures two CMOS inverters connected to a power line VDD and a ground line VSS, and holds data of one bit by positive feedback of cross-couple connection of the inverter pair. A transfer transistor MTB is connected to a bit line BLB via a write transistor MWB2 that is shared by two bits. A read transistor MRT and a write transistor MWT are connected to a bit line BLT side via a transfer transistor MTT. By sharing transistors between adjacent cells using the path of write, the number of transistors is reduced.
Bibliography:Application Number: JP20090159413