IMPEDANCE ADJUSTMENT CIRCUIT

PROBLEM TO BE SOLVED: To provide an impedance adjustment circuit which materializes optimization of impedance at an input buffer end of a transmission path.SOLUTION: This impedance adjustment circuit 100 includes a first input buffer 4 for detecting that an input signal exceeds a VREFA 6, a second i...

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Bibliographic Details
Main Author NAKATSU ISAO
Format Patent
LanguageEnglish
Published 06.01.2011
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PULSE TECHNIQUE
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:PROBLEM TO BE SOLVED: To provide an impedance adjustment circuit which materializes optimization of impedance at an input buffer end of a transmission path.SOLUTION: This impedance adjustment circuit 100 includes a first input buffer 4 for detecting that an input signal exceeds a VREFA 6, a second input buffer 5 for detecting that an input signal exceeds a VREFA 7 higher than the VREFA 6, a counter circuit A10 for performing counting based on an output of the first input buffer 4, a counter circuit B11 for performing counting based on an output of the second input buffer 5, and a terminal resistor control circuit 19 for controlling impedance of a terminal resistor 3 provided at a terminal of a transmission path based on a counting result by a counter of the counter circuit A10 and a counting result by the counter circuit B11.
Bibliography:Application Number: JP20090146177