FIELD EFFECT TRANSISTOR

• Main Authors: NAKAZAWA TOSHI, UEDA TETSUZO
• Format: Patent
• Language: English
• Published: 24.12.2010
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To provide a field effect transistor which has small parasitic resistance while actualizing normally off operation. SOLUTION: The field effect transistor includes a buffer layer 2 formed on a substrate 1 and made of GaN, an electron supply layer 3 formed on the buffer layer 2 and made of InxAlyAg1-x-yN (where 0≤x≤1, 0≤y≤1, and 0<x+y≤1), and a cap layer 4 which is formed on the electron supply layer 3 and has a different composition from the electron supply layer 3, to which an n-type impurity of high concentration is added, and which is made of InsAltAg1-s-tN (where 0≤s≤1, 0≤t≤1, and 0<s+t≤1). A recess 4a is formed in the cap layer 4, a source electrode 5 and a drain electrode 7 are formed in both regions by the recess 4a in the cap layer 4, and a gate electrode 6 is formed at the recess 4a in the cap layer 4 with the insulating film 8 interposed. COPYRIGHT: (C)2011,JPO&INPIT