SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide an SRAM (semiconductor memory) having large soft error resistivity. SOLUTION: In a full CMOSSRAM in which, a first and second driver MOS transistors N1, N2, a first and second load MOS transistors P1, P2, and a first and second access NMOS transistors N3, N4 are prep...

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Bibliographic Details
Main Author YOKOYAMA TAKEHIRO
Format Patent
LanguageEnglish
Published 19.08.2010
Subjects
ELECTRICITY
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Summary:PROBLEM TO BE SOLVED: To provide an SRAM (semiconductor memory) having large soft error resistivity. SOLUTION: In a full CMOSSRAM in which, a first and second driver MOS transistors N1, N2, a first and second load MOS transistors P1, P2, and a first and second access NMOS transistors N3, N4 are prepared on an oblong type cell (a memory cell in which a well divided into three is lined in the direction of extending of a word line and is longer in the word line direction than in the bit line direction), buried wirings 5D, 5G to become a storage node include slopes 50D, 50G extending in the direction intersecting the longitudinal direction of polysilicon interconnections 3C, 3B. COPYRIGHT: (C)2010,JPO&INPIT
Bibliography:Application Number: JP20100122734