SEMICONDUCTOR MEMORY

PROBLEM TO BE SOLVED: To provide a semiconductor memory to which a charge capacitor for countering software errors can be added without increasing a cell area. SOLUTION: In the semiconductor memory including a plurality of full CMOS memory cells disposed in an array, a first driver transistor compri...

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Bibliographic Details
Main Authors ISHIGAKI YOSHIYUKI, OBAYASHI SHIGEKI, YOKOYAMA TAKEHIRO
Format Patent
LanguageEnglish
Published 08.07.2010
Subjects
ELECTRICITY
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Summary:PROBLEM TO BE SOLVED: To provide a semiconductor memory to which a charge capacitor for countering software errors can be added without increasing a cell area. SOLUTION: In the semiconductor memory including a plurality of full CMOS memory cells disposed in an array, a first driver transistor comprises a first active layer 11A and a first gate line 12A, and a first access transistor comprises the first active layer 11A and a third gate line 12C, and a first load transistor comprises a second active layer 11B and the first gate line 12A, and a second load transistor comprises a third active layer 11C and a fourth gate line 12D. and a second driver transistor comprises a fourth active layer 11D and the fourth gate line 12D, and a second access transistor comprises the fourth active layer 11D and a second gate line 12B, and a charge capacitance comprises a fifth contact line 13E and a conductive film and comprise a sixth contact line 13F and the conductive film. COPYRIGHT: (C)2010,JPO&INPIT
Bibliography:Application Number: JP20100033372