PLL CIRCUIT AND METHOD OF CONTROLLING THE SAME

• Main Author: KAWASHIMA TOSHITSUGU
• Format: Patent
• Language: English
• Published: 17.06.2010
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; ELECTRICITY

PROBLEM TO BE SOLVED: To solve such a problem that the conventional PLL (Phase Locked Loop) circuit can not stably control an oscillation frequency in good precision. SOLUTION: The PLL circuit includes: a PFD (Phase-Frequency Detector) 401 that detects a phase difference between two clock signals; an LPF (Loop Filter) 403 that outputs voltage 404 based on the detection results of the PFD 401; a VCO (Voltage Controlled Oscillator) 405 that controls a frequency of a VCO output clock 406 which is output based on the voltage 404; a frequency divider 407 that divides a frequency of the VCO output clock 406 and outputs an output clock 408; and an automatic adjustment circuit 411 that adjusts a frequency division ratio of the frequency divider 407 based on the voltage 404. Moreover, the automatic adjustment circuit 411 prepares: a comparison circuit 434 that outputs a control signal 419 for controlling the frequency divider 407 and a control signal 420 for controlling the reference voltage; and a reference voltage selector 413. COPYRIGHT: (C)2010,JPO&INPIT