CONTROL APPARATUS AND CLOCK SYNCHRONIZING METHOD

• Main Author: ATAMI TAKESHI
• Format: Patent
• Language: English
• Published: 03.06.2010
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; PULSE TECHNIQUE

PROBLEM TO BE SOLVED: To suppress occurrence of a phase jump of an output clock caused by an instantaneous phase jump of an input clock in a DPLL (digital phase locked loop) circuit. SOLUTION: A control apparatus that performs control to synchronize an output clock signal with an input clock signal includes: a counting part that counts a phase difference between the input clock signal and the output clock signal; an extracting part that extracts a count value indicating, of phase differences counted by the counting part, a phase difference within a certain range; a phase difference information generating part that generates phase difference information on the basis of the extracted count value indicating the phase difference within the certain range; and a clock generation part capable of controlling a frequency of the output clock signal to be generated on the basis of the phase difference information generated by the phase difference information generating part. COPYRIGHT: (C)2010,JPO&INPIT