SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit and a layout method of a semiconductor integrated circuit, in which a power supply line pattern is reinforced without disturbing signal wiring in an upper layer. SOLUTION: The layout method of a semiconductor integrated circuit incl...

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Bibliographic Details
Main Author KOBAYAKAWA OSAMU
Format Patent
LanguageEnglish
Published 04.02.2010
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit and a layout method of a semiconductor integrated circuit, in which a power supply line pattern is reinforced without disturbing signal wiring in an upper layer. SOLUTION: The layout method of a semiconductor integrated circuit includes: a base layer in which a logic device is prepared; and an upper layer prepared on the base layer. The method also includes steps of: laying out two or more power supply lines prolonged on the upper layer and generating power supply line data, and laying out the logic device on the base layer and generating logic device data; and a laying out a conductive pattern for power supply reinforcement based on the power supply line data and the logic device data and generating pattern data for power supply reinforcement. The step of generating the pattern data for power supply reinforcement includes a step of laying out the pattern for power supply reinforcement in a region in which the logic device is not laid out in the base layer so that the two or more prolonged power supply line patterns are connected together. COPYRIGHT: (C)2010,JPO&INPIT
Bibliography:Application Number: JP20080190281