SCAN TEST CIRCUIT AND SCAN TEST METHOD

PROBLEM TO BE SOLVED: To provide a scan test circuit with a multiplication circuit for performing a test by changing the speed of a clock by N-multiplication, and to provide a scan test method. SOLUTION: This scan test circuit includes: a multiplication circuit 8 for performing a test by changing th...

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Bibliographic Details
Main Authors NISHIGAKI NAOHIKO, TOKAWA YUKIO
Format Patent
LanguageEnglish
Published 04.02.2010
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PROBLEM TO BE SOLVED: To provide a scan test circuit with a multiplication circuit for performing a test by changing the speed of a clock by N-multiplication, and to provide a scan test method. SOLUTION: This scan test circuit includes: a multiplication circuit 8 for performing a test by changing the speed of a clock by N multiplication; a low speed to high speed operation circuit 10 for changing the speed of defrosted data by N times from an external chain by using an N time clock created by the multiplication circuit; and a high speed to low speed operation circuit 11 for changing the speed of a clock by using an N time clock created by the multiplication circuit 8 so that data from a core logic can be matched with the speed of an external clock, and configured to compress the data of an internal chain by using the external clock, and to perform expected value comparison by using the speed of the external clock. COPYRIGHT: (C)2010,JPO&INPIT
Bibliography:Application Number: JP20080186335