METHOD FOR MANUFACTURING WIRING BOARD

PROBLEM TO BE SOLVED: To provide a method for manufacturing a wiring board for forming a resist film for plating on a seed layer arranged on an insulating layer, and for forming wiring on the seed layer by an electrolytic plating method with the seed layer as a feeder layer, wherein it is possible t...

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Bibliographic Details
Main Author KOJIMA HIRONARI
Format Patent
LanguageEnglish
Published 05.11.2009
Subjects
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
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Summary:PROBLEM TO BE SOLVED: To provide a method for manufacturing a wiring board for forming a resist film for plating on a seed layer arranged on an insulating layer, and for forming wiring on the seed layer by an electrolytic plating method with the seed layer as a feeder layer, wherein it is possible to prevent a resist film for plating from being peeled from the seed layer, and to shorten an etching time in removing an unnecessary seed layer, and to form wiring so that the size of wiring after a seed layer removal process can be set to a prescribed size. SOLUTION: A seed layer 12 is formed so that a smooth upper face 11A of an insulating layer 11 can be covered, and an upper face 12A of the seed layer 12 is roughened, and a resist film 15 for plating which has an opening 15A exposing an upper face 12A of the seed layer 12 of the section corresponding to the formation region of the wiring 13 is formed, and wiring 13 is formed on the upper face 12A of the seed layer 12 by an electrolytic plating method with the seed layer 12 as a feeder layer, and a resist film 15 for plating is removed, and an unnecessary seed layer 12 of the section where the wiring 13 is not formed is removed. COPYRIGHT: (C)2010,JPO&INPIT
Bibliography:Application Number: JP20080223635