OPTIMIZED CIRCUIT DESIGN LAYOUT FOR HIGH PERFORMANCE BALL GRID ARRAY PACKAGES

• Main Authors: NOZAR HASSANZADEE, STEARNS WILLIAM P
• Format: Patent
• Language: English
• Published: 15.10.2009
• Subjects: BASIC ELECTRIC ELEMENTS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS; PRINTED CIRCUITS; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To provide a method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board, or the like, and the layout thereof. SOLUTION: A substrate 1 has top and bottom surfaces with a plurality of rows and columns of vias 11, extending therethrough from the top surface to the bottom surface, and has a solder ball 13 secured at the bottom surface to each via. A plurality of pairs of traces 9 is provided on the top surface, with each trace of each pair of traces extending to a different one of the vias and extending to vias on a plurality of the rows and columns, each of the traces of each pair being spaced from the other trace by a ball pitch, being maximized for identity in length and being maximized for parallelism and spacing. Each of the traces of a pair, preferably, be further maximized for identity in cross-sectional geometry. A differential signal pair is, preferably, applied to at least one of a pair of traces. The layout can further include a further surface between the top and bottom surfaces which is insulated from the top and bottom surfaces, a plurality of the traces being disposed on the further surface. COPYRIGHT: (C)2010,JPO&INPIT