INTERRUPTION MANAGEMENT MECHANISM AND MICROCOMPUTER

PROBLEM TO BE SOLVED: To reduce the number of execution times of interruption processing in a CPU and to improve the processing efficiency of the CPU. SOLUTION: In a microcomputer (10) for executing data transfer between the CPU (20) and a memory (60) through a serial interface (50), an interruption...

Full description

Saved in:
Bibliographic Details
Main Authors FUJITA ATSUSHI, TOMATSURI HIDEAKI, AKASHI MASANORI
Format Patent
LanguageEnglish
Published 23.07.2009
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:PROBLEM TO BE SOLVED: To reduce the number of execution times of interruption processing in a CPU and to improve the processing efficiency of the CPU. SOLUTION: In a microcomputer (10) for executing data transfer between the CPU (20) and a memory (60) through a serial interface (50), an interruption management mechanism (40) for managing an interruption request of the serial interface (50) includes state transition circuits (42f, 42g) and an interruption request issue circuit (42). The state transition circuits (42f, 42g) transit their states according to a sort of the interruption request and the number of issues in accordance with the issue of the interruption request from the serial interface (50). The interruption request issue circuit (42) issues an interruption request to the CPU (20) when the states of the state transition circuits (42f, 42g) are transited to prescribed states. COPYRIGHT: (C)2009,JPO&INPIT
Bibliography:Application Number: JP20080000990