SEMICONDUCTOR DEVICE

• Main Authors: HATAMOTO MITSUO, MATSUMIYA YOSHIAKI
• Format: Patent
• Language: English
• Published: 12.02.2009
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To solve a problem that although a J-FET has a distance made larger between a drain region and a gate region than between a source region and the gate region in the case of a striped shape because of a difference in depletion layer width depending upon the relation between a gate-source voltage and a drain-source voltage, gate regions are at an equal distance when disposed in a grating shape because of improvement in forward transfer admittance gm, and box area increases for maintaining a breakdown voltage. SOLUTION: A gate region is formed in a net-shaped pattern having a first polygonal shape and a second polygonal shape smaller than the first polygonal shape, and a source region and a drain region are arranged inside the pattern. Consequently, the forward transfer admittance gm can be increased as compared with a structure having gate regions arranged in stripes. Further, while a prescribed breakdown voltage is maintained, deterioration in forward transfer characteristics (amplification characteristics) due to an increase in input capacity Ciss can be minimized as compared with a case wherein gate regions are arranged in a grating shape. COPYRIGHT: (C)2009,JPO&INPIT