INFORMATION PROCESSOR AND ACCESS CONTROL METHOD
PROBLEM TO BE SOLVED: To perform accurate time-out determination in an information processor which performs access arbitration in the event of competition of accesses from a plurality of buses. SOLUTION: The information processor comprises a first bus 10A having a first bus master 20 and a counter 1...
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Main Author | |
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Format | Patent |
Language | English |
Published |
11.12.2008
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Subjects | |
Online Access | Get full text |
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Summary: | PROBLEM TO BE SOLVED: To perform accurate time-out determination in an information processor which performs access arbitration in the event of competition of accesses from a plurality of buses. SOLUTION: The information processor comprises a first bus 10A having a first bus master 20 and a counter 16A for detecting a time-out time of this bus master; a second bus 12B having a second bus master 22 and a counter 16B for detecting a time-out time of this bus master; and an access arbitration device 28 connected between a memory 30 and the first and second buses, which permits the access request from one of the first and second buses when access requests from the first and second buses complete, makes the access request from the other bus stand by until the permitted access request is completed, and supplies a report signal for reporting the standby state to the other bus. Each of the first and second bus counters starts counting when the first or second bus generates the access request, and stops counting when the report signal is supplied. COPYRIGHT: (C)2009,JPO&INPIT |
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Bibliography: | Application Number: JP20070145805 |