METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To improve the reliability of a solder joint between a semiconductor chip and the other composition member, and the reliability of a solder joint between composition materials other than the semiconductor chip. SOLUTION: A solder joint layer 5 is heated and melted in a state th...

Full description

Saved in:
Bibliographic Details
Main Authors MOCHIZUKI EIJI, IKEDA YOSHINARI, YAMASHITA MITSUO, FUJII TAKASHI, IIZUKA YUJI, YOSHIHARA KATSUHIKO
Format Patent
LanguageEnglish
Published 06.11.2008
Subjects
Online AccessGet full text

Cover

Loading…
Abstract PROBLEM TO BE SOLVED: To improve the reliability of a solder joint between a semiconductor chip and the other composition member, and the reliability of a solder joint between composition materials other than the semiconductor chip. SOLUTION: A solder joint layer 5 is heated and melted in a state that a filler thinner than the solder joint layer 5 before melted is placed on the solder joint layer 5 before melting, and then the solder joint layer 5 is cooled and hardened in a state that the filler drips into the melted solder joint layer 5. This can set the thickness of the solder joint layer 5 with which a heat sink 6 and an insulating substrate 3 are joined to a desired thickness, and makes the filler as a spacer, to reduce distortion generated in the solder joint layer 5. Furthermore, in a similar way in a solder joint between the semiconductor chip and a lead frame and in a solder joint between the insulating substrate 3 and the semiconductor chip, this makes the fillers as spacers in solder joint layers which connect them to each other, to reduce distortion generated in the solder joint layers. COPYRIGHT: (C)2009,JPO&INPIT
AbstractList PROBLEM TO BE SOLVED: To improve the reliability of a solder joint between a semiconductor chip and the other composition member, and the reliability of a solder joint between composition materials other than the semiconductor chip. SOLUTION: A solder joint layer 5 is heated and melted in a state that a filler thinner than the solder joint layer 5 before melted is placed on the solder joint layer 5 before melting, and then the solder joint layer 5 is cooled and hardened in a state that the filler drips into the melted solder joint layer 5. This can set the thickness of the solder joint layer 5 with which a heat sink 6 and an insulating substrate 3 are joined to a desired thickness, and makes the filler as a spacer, to reduce distortion generated in the solder joint layer 5. Furthermore, in a similar way in a solder joint between the semiconductor chip and a lead frame and in a solder joint between the insulating substrate 3 and the semiconductor chip, this makes the fillers as spacers in solder joint layers which connect them to each other, to reduce distortion generated in the solder joint layers. COPYRIGHT: (C)2009,JPO&INPIT
Author FUJII TAKASHI
IKEDA YOSHINARI
YOSHIHARA KATSUHIKO
MOCHIZUKI EIJI
IIZUKA YUJI
YAMASHITA MITSUO
Author_xml – fullname: MOCHIZUKI EIJI
– fullname: IKEDA YOSHINARI
– fullname: YAMASHITA MITSUO
– fullname: FUJII TAKASHI
– fullname: IIZUKA YUJI
– fullname: YOSHIHARA KATSUHIKO
BookMark eNrjYmDJy89L5WTQ9XUN8fB3UXDzD1LwdfQLdXN0DgkN8vRzVwh29fV09vdzCXUOAcq5uIZ5OrvyMLCmJeYUp_JCaW4GJTfXEGcP3dSC_PjU4oLE5NS81JJ4rwAjAwMLI3MDCxMzR2OiFAEAECcn2w
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
ExternalDocumentID JP2008270846A
GroupedDBID EVB
ID FETCH-epo_espacenet_JP2008270846A3
IEDL.DBID EVB
IngestDate Fri Jul 19 14:45:32 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_JP2008270846A3
Notes Application Number: JP20080207415
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20081106&DB=EPODOC&CC=JP&NR=2008270846A
ParticipantIDs epo_espacenet_JP2008270846A
PublicationCentury 2000
PublicationDate 20081106
PublicationDateYYYYMMDD 2008-11-06
PublicationDate_xml – month: 11
  year: 2008
  text: 20081106
  day: 06
PublicationDecade 2000
PublicationYear 2008
RelatedCompanies FUJI ELECTRIC DEVICE TECHNOLOGY CO LTD
RelatedCompanies_xml – name: FUJI ELECTRIC DEVICE TECHNOLOGY CO LTD
Score 2.7237906
Snippet PROBLEM TO BE SOLVED: To improve the reliability of a solder joint between a semiconductor chip and the other composition member, and the reliability of a...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20081106&DB=EPODOC&locale=&CC=JP&NR=2008270846A
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_mFPVNp6JOpYj0rdhtXVofinRJSi30A23H3kazZSDCHK7iv-8lrLqnvYUcXJKDy-_ucpcDeBAzTxCnmllztPUth6ANJ5xeZSG2CE_aRNpSFScnKYlKJ54MJy34aGph9D-hP_pzRNSoGep7re_r1X8Qi-ncyvWjeMepz-ew8JnZeMceohkx2cjnecYyalLqx7mZvmpa37URbYM92Ec72lX5X3w8UmUpq21MCU_gIEd2y_oUWnLZgSPatF7rwGGyefHG4Ub51mdgJbyIMmag32YkQVqGAS1KlcxgvClhZikraYE0xscvlJ_DfcgLGlm47vTvlNM439rj4ALa6P7LSzCeqkXVI-4CobtCxFH9Hud9zxtKgTjjDJwr6O5gdL2T2oVjnf-gwqTkBtr117e8RZCtxZ0Wzi81-nrX
link.rule.ids 230,309,783,888,25578,76884
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_mFOebTkWdH0Wkb8Vu67L6UGRLWrq6fqDt2FtpugxEmMNV_Pe9hE33tLeQg0tycPndJfcB8MBLmxOrKI0Z2vqGRdCG41a7MBBbuC1MIkwhk5PDiPiZFUx70xp8bHJhVJ3QH1UcETWqRH2v1H29_H_EYiq2cvXI33Hq89lLHaZvvGMb0YzobOi4ScxiqlPqBIkevSpap28i2g72YB9tbFsW2ncnQ5mWstzGFO8YDhJkt6hOoCYWTWjQTeu1JhyG6x9vHK6Vb3UKRuimfsw09Nu0cBBl3oCmmQxm0N6kMOOIZTRFGnMnI-qewb3nptQ3cN3875R5kGztsXsOdXT_xQVoT8W8aJP-HKG7QMSR_R5nHdvuCY44Y3WtS2jtYHS1k3oHDT8Nx_l4FL204EjFQsgnU3IN9errW9wg4Fb8VgnqFyBUfcc
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=METHOD+FOR+MANUFACTURING+SEMICONDUCTOR+DEVICE&rft.inventor=MOCHIZUKI+EIJI&rft.inventor=IKEDA+YOSHINARI&rft.inventor=YAMASHITA+MITSUO&rft.inventor=FUJII+TAKASHI&rft.inventor=IIZUKA+YUJI&rft.inventor=YOSHIHARA+KATSUHIKO&rft.date=2008-11-06&rft.externalDBID=A&rft.externalDocID=JP2008270846A