SEMICONDUCTOR WAFER AND RETICLE AS WELL AS METHOD OF EXPOSURE EMPLOYING THE RETICLE

• Main Authors: HARUKI TORU, NISHIHARA KENJI, MIYAKE HIDEJI, SAGAWA KOICHI
• Format: Patent
• Language: English
• Published: 04.09.2008
• Subjects: APPARATUS SPECIALLY ADAPTED THEREFOR; BASIC ELECTRIC ELEMENTS; CINEMATOGRAPHY; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; ELECTROGRAPHY; HOLOGRAPHY; MATERIALS THEREFOR; ORIGINALS THEREFOR; PHOTOGRAPHY; PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES; PHYSICS; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To improve an yield by making the electrical characteristics of device chips uniformize, formed at the vicinity of forming region of an alignment mark for positioning a semiconductor wafer and other device chips formed in other regions. SOLUTION: The semiconductor wafer 2 is provided with a plurality of device chip regions 4 formed in the plane of a substrate having multi-layers wiring structure, scribe lines 8 formed in the circumference of the device chip regions 4, in order to separate the device chip region 4 respectively and blank regions 6. The blank regions 6 comprise at least one alignment region 10 and the alignment mark is constituted of a metal film pattern on the uppermost layer surface of the alignment region 10. The alignment region 10 is provided with a size same as the device chip region 4 and patterns identical to the patterns formed on the same layer of the device chip region 4 are formed on the wiring layers below the uppermost layer, while a metal film which serves as the alignment mark is formed on the uppermost layer. COPYRIGHT: (C)2008,JPO&INPIT