VERIFYING CONTROL SCHEME FOR SEMICONDUCTOR MEMORY AND METHOD THEREOF

PROBLEM TO BE SOLVED: To provide a verifying control scheme and method thereof for avoiding over stress onto memory cells due to program operation in a memory operation mode without verification of a flash memory before programming. SOLUTION: A verifying control scheme of the semiconductor memory co...

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Bibliographic Details
Main Authors TSUKIDATE YOSHIHIRO, SENOO SHINGEN, TOYAMA SHUNICHI, KIDO KAZUNARI
Format Patent
LanguageEnglish
Published 10.01.2008
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PROBLEM TO BE SOLVED: To provide a verifying control scheme and method thereof for avoiding over stress onto memory cells due to program operation in a memory operation mode without verification of a flash memory before programming. SOLUTION: A verifying control scheme of the semiconductor memory comprises a memory section 10 including a plurality of memory cells; a verifying section 20 for judging programming status of memory cells of the memory section 10; and an address/program control section 30 that controls the memory section 10 and the verifying section 20, enters suspend operation while executing a program operation to the memory cells, and starts the verify operation when the suspend operation ends. In the memory operation mode without verification before programming, the address/program control section 30 restarts the program operation when the memory cell needs rewriting as a result of the verification operation, and takes control of the next address memory cells for executing the program operation if unnecessary. COPYRIGHT: (C)2008,JPO&INPIT
Bibliography:Application Number: JP20060175550