SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit improving malfunction detection rate of a memory cell peripheral circuit at low power consumption. SOLUTION: The semiconductor integrated circuit coping with scan test including scan cells 302, 316 for application of a test signal,...

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Bibliographic Details
Main Author SATOI TOMOKI
Format Patent
LanguageEnglish
Published 18.10.2007
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
SEMICONDUCTOR DEVICES
TESTING
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Summary:PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit improving malfunction detection rate of a memory cell peripheral circuit at low power consumption. SOLUTION: The semiconductor integrated circuit coping with scan test including scan cells 302, 316 for application of a test signal, scan cells 307, 319 for outputting the test signal, and a memory cell 301 includes a bypass path circuit 317 that is a circuit between an input terminal and an output terminal of the memory cell 301 and provided outside the memory cell 301, a mode setting means 60 for setting the memory cell 301 into a transparent mode or a bypass path mode, and a selection means 65 for selecting an output of the bypass path circuit 317 and an output of the memory cell 301 set by the mode setting means 60. COPYRIGHT: (C)2008,JPO&INPIT
Bibliography:Application Number: JP20060094901