IMAGE DECODING APPARATUS

• Main Authors: OGAMI AKIHIRO, UEHASHI MASASHI, MICHINAKA HIDEJI, OGAWA TAKAYA, TAKEGAWA SATOSHI, SHIGETA YOSHINORI, NAKAYAMA HIROMITSU, SUZUMURA TATSUHIRO, WATANABE KIWAMU
• Format: Patent
• Language: English
• Published: 04.10.2007
• Subjects: BASIC ELECTRONIC CIRCUITRY; CODE CONVERSION IN GENERAL; CODING; DECODING; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; PICTORIAL COMMUNICATION, e.g. TELEVISION

PROBLEM TO BE SOLVED: To provide an image decoding apparatus capable of performing arithmetic coding/decoding processing, performing a plurality of different decoding processes following the arithmetic coding/decoding processing through pipeline processing for a predetermined data unit, and further performing image decoding processing with a little buffer memory capacity without rupture. SOLUTION: The image decoding apparatus comprises an arithmetic coding/decoding unit 102, a variable length coding/decoding unit 112, and a shared buffer memory 106. The arithmetic coding/decoding unit 102 inputs arithmetically coded image data and outputs a code stream being binarized only by decoding arithmetic codes of the arithmetically coded image data. The variable length coding/decoding unit 112 performs variable length coding/decoding on the code stream outputted from the arithmetic coding/decoding unit 102. The buffer memory 106 is a shared memory that is composed of a DRAM, for example, and exchanges (delivers) data between the arithmetic coding/decoding unit 102 and the variable length coding/decoding unit 112. COPYRIGHT: (C)2008,JPO&INPIT