DATA PROCESSOR

PROBLEM TO BE SOLVED: To enable restart to a state that an operation reference clock signal is stopped to lapse into a deadlock without performing power-on reset. SOLUTION: This data processor (2) has: a system clock generation circuit (35) generating a system clock 1; a system control circuit (22);...

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Bibliographic Details
Main Authors TANIGUCHI KAZUYA, WADA TARO
Format Patent
LanguageEnglish
Published 07.06.2007
Subjects
BLASTING
CALCULATING
COMBUSTION ENGINES
COMPUTING
CONTROLLING COMBUSTION ENGINES
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
HEATING
HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
LIGHTING
MECHANICAL ENGINEERING
PHYSICS
WEAPONS
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Summary:PROBLEM TO BE SOLVED: To enable restart to a state that an operation reference clock signal is stopped to lapse into a deadlock without performing power-on reset. SOLUTION: This data processor (2) has: a system clock generation circuit (35) generating a system clock 1; a system control circuit (22); and an interrupt control circuit (24). The interrupt control circuit inverts a clock stop signal (OSCSTP) outputted from the system control circuit, stopping the system clock when interrupt requirement is given by external interrupt requirement signals (IRQ1, IRQ2) in a standby state and when interrupt masking by corresponding interrupt masking signals (IRQ1E, IRQ2E) is not performed. When the interrupt masking is performed, the interrupt control circuit changes an interrupt masking instruction of the interrupt masking signals by the fed-back clock stop signal, and releases an instruction of the stop of the system clock. COPYRIGHT: (C)2007,JPO&INPIT
Bibliography:Application Number: JP20050329829