DELAY ADJUSTING CIRCUIT AND SYNCHRONOUS TYPE SEMICONDUCTOR DEVICE EQUIPPED WITH THE CIRCUIT

• Main Authors: KUROKI KOJI, FUJISAWA HIROKI
• Format: Patent
• Language: English
• Published: 15.03.2007
• Subjects: BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; PULSE TECHNIQUE

PROBLEM TO BE SOLVED: To provide a delay adjusting circuit capable of finely adjusting a delay time by shortening a propagation delay time. SOLUTION: The delay adjusting circuit is equipped with a first group of parallel-connected transistors PM2-1 to PM2-3 which input control signals A, C, D respectively at their gates between a PMOS transistor PM1 constituting an inverter and a power source Vcc and also equipped with a 2nd group of parallel-connected transistors NM2-1 to NM2-3 which input control signals respectively at their gates and an inverter 2 which inputs the output of the inverter 1 between an NMOS transistor NM1 constituting an inverter and a GND, and at least one of the transistors PM2-1 to PM2-3 of the first group and at least one of the transistors NP2-1 to NM2-3 of the second group are set into ON states. COPYRIGHT: (C)2007,JPO&INPIT