SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

PROBLEM TO BE SOLVED: To permit the suppression of a parasitic capacitance between wirings even when deviation of alignment of mask patterns arises upon forming via holes. SOLUTION: A wiring layer 5 is formed so that upper surface is positioned below a silicon nitride film 6 formed on the surface of...

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Bibliographic Details
Main Authors KAWABATA ITARU, INOUE HIROFUMI
Format Patent
LanguageEnglish
Published 26.10.2006
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PROBLEM TO BE SOLVED: To permit the suppression of a parasitic capacitance between wirings even when deviation of alignment of mask patterns arises upon forming via holes. SOLUTION: A wiring layer 5 is formed so that upper surface is positioned below a silicon nitride film 6 formed on the surface of an interlayer dielectric 4. According to this method, a distance between a via plug 8 and the neighboring wiring layer 11 can be kept long even if the deviation of alignment arises. COPYRIGHT: (C)2007,JPO&INPIT
Bibliography:Application Number: JP20050115728