SIMULATION METHOD

PROBLEM TO BE SOLVED: To provide a simulation method capable of reducing the time to verify the logic operations of LSI by automatically creating a data input/output circuit between an untimed operation model and a mounted logic circuit. SOLUTION: The simulation method includes a step in which a mou...

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Bibliographic Details
Main Author TAKEI TSUTOMU
Format Patent
LanguageEnglish
Published 16.02.2006
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:PROBLEM TO BE SOLVED: To provide a simulation method capable of reducing the time to verify the logic operations of LSI by automatically creating a data input/output circuit between an untimed operation model and a mounted logic circuit. SOLUTION: The simulation method includes a step in which a mounting part creates data on the logic circuit mountable in a rewritable semiconductor device in order to execute the logic operations achieved by hardware; a step in which the mounting part creates data on the input/output circuit mountable in the semiconductor device in order to execute input/output operations included in the logic operations achieved by software; and a step in which a verifying part verifies the logic operations of a semiconductor integrated circuit using the logic circuit mounted in the semiconductor device according to the logic circuit data, the input/output circuit mounted in the semiconductor device according to the input/output circuit data, and the untimed operation model for executing the logic operations achieved by the software, the untimed operation model having no time setting description. COPYRIGHT: (C)2006,JPO&NCIPI
Bibliography:Application Number: JP20040231289