LAYOUT DESIGN SYSTEM AND LAYOUT-DESIGNING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To solve the problem wherein the deviations in the consumption-current distribution, when a consumption current is increased partially on a semiconductor integrated circuit, has not been taken into consideration by layout designing methods. SOLUTION: In the layout designing met...

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Bibliographic Details
Main Author OKADA NOBUYA
Format Patent
LanguageEnglish
Published 26.01.2006
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:PROBLEM TO BE SOLVED: To solve the problem wherein the deviations in the consumption-current distribution, when a consumption current is increased partially on a semiconductor integrated circuit, has not been taken into consideration by layout designing methods. SOLUTION: In the layout designing method for a semiconductor integrated circuit, a power connecting cell electrically connecting an uppermost-layer wiring and a lower-layer wiring is arranged. The layout designing method has a process, in which the arrangement of a plurality of functional blocks on the semiconductor integrated circuit is set, and the process in which a plurality of the power-connecting cells are disposed in a semiconductor integrated-circuit forming region on the outsides of functional-block arranging regions. The layout designing method further has a process, in which the effect of the voltage drop of the uppermost-layer wiring is analyzed on the basis of the disposal of the power connecting cells. COPYRIGHT: (C)2006,JPO&NCIPI
Bibliography:Application Number: JP20040200268