DELAY SIGNAL GENERATOR CIRCUIT AND MEMORY SYSTEM INCLUDING THE SAME
PROBLEM TO BE SOLVED: To provide a circuit capable of generating a stable delay signal using an inverter chain regardless of changes in process, voltage and temperature, and memory system including the same. SOLUTION: A delay signal generator circuit includes a delay circuit and a delay control circ...
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Main Author | |
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Format | Patent |
Language | English |
Published |
04.08.2005
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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Summary: | PROBLEM TO BE SOLVED: To provide a circuit capable of generating a stable delay signal using an inverter chain regardless of changes in process, voltage and temperature, and memory system including the same. SOLUTION: A delay signal generator circuit includes a delay circuit and a delay control circuit. The delay circuit sequentially delays a first clock signal to generate a plurality of delay signals and outputs one of the delay signals. The delay control circuit samples the outputted delay signal in response to a transition of a second clock signal having twice a frequency of the first clock signal, and controls the delay circuit based upon the sampled value so that the outputted delay signal has an increased/decreased delay time. COPYRIGHT: (C)2005,JPO&NCIPI |
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Bibliography: | Application Number: JP20050005477 |