SEMICONDUCTOR MEMORY DEVICE

PROBLEM TO BE SOLVED: To solve the problem that a replica circuit in a conventional mask ROM sometimes malfunctions due to a variation in operation caused by a variation in manufacturing, etc. which causes the replica circuit to finish its operation before the operation of a sense amplifier finishes...

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Bibliographic Details
Main Authors KURATA KATSUICHI, NAKAYA SHUJI
Format Patent
LanguageEnglish
Published 07.07.2005
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:PROBLEM TO BE SOLVED: To solve the problem that a replica circuit in a conventional mask ROM sometimes malfunctions due to a variation in operation caused by a variation in manufacturing, etc. which causes the replica circuit to finish its operation before the operation of a sense amplifier finishes, and that a layout area is enlarged when a margin is secured by using a plurality of dummy bit lines. SOLUTION: In a dummy memory cell array of the semiconductor memory device, metal electrodes connected to contacts and via-holes 28, 29, and 30 for connecting a drain region (21) to the dummy bit lines 25 are connected to metal electrodes of the dummy memory cells adjacent in the bit line direction respectively to form metal interconnections 34 and 35 which are arranged in parallel to the dummy bit lines 25. By this structure, the parasitic capacitance of the dummy bit lines 25 is increased, and hence a timing margin can be secured even if the number of the dummy bit lines 25 is reduced, resulting in suppressing an increase in layout area. COPYRIGHT: (C)2005,JPO&NCIPI
Bibliography:Application Number: JP20030419587