NONVOLATILE SEMICONDUCTOR MEMORY, ITS WRITE METHOD AND ERASE METHOD

• Main Authors: TAMAI YUKIO, INOUE TAKESHI, MORITA TERUAKI
• Format: Patent
• Language: English
• Published: 03.02.2005
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory having variable resistive elements in which generation of disturbance is suppressed, high integration is easily realized and resistance values are reversibly varied by applying a voltage. SOLUTION: In a memory array 1, one end of each variable resistive element 22 located in the same row is connected to the same word line and the other end of each variable resistive element 22 located in the same column is connected to the same bit line. A first word line voltage is selected and applied to the selected word line, and a second word line voltage is selected and applied to the unselected word lines. A first bit line voltage is selected and applied to the selected bit line, and a second bit line voltage is selected and applied to the unselected bit lines. The voltage difference between the first word line voltage and the first bit line voltage is set at a value that is no less than the fist voltage difference that changes the resistance value of the variable resistive element. The voltage difference between the first word line voltage and the second bit line voltage, the voltage difference between the second word line voltage and the first bit line voltage and the voltage difference between the second word line voltage and the second bit line voltage are respectively set at a value that is no greater than the second voltage difference which does not change the resistance value of a variable resistive element. COPYRIGHT: (C)2005,JPO&NCIPI