MEMORY ELEMENT USING NANOTUBE

PROBLEM TO BE SOLVED: To provide a highly integrated large capacity memory element using nanotubes. SOLUTION: This memory element comprises an array of first electrodes 11 which are formed in a stripe pattern, a dielectric layer 12 which is laminated on the array of the first electrodes 11 and in wh...

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Bibliographic Details
Main Authors CHOI WON-BONG, CHEONG BYOUNG-HO
Format Patent
LanguageEnglish
Published 04.11.2004
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
MANUFACTURE OR TREATMENT THEREOF
NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS,MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES ASDISCRETE UNITS
NANOTECHNOLOGY
PERFORMING OPERATIONS
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
TRANSPORTING
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Summary:PROBLEM TO BE SOLVED: To provide a highly integrated large capacity memory element using nanotubes. SOLUTION: This memory element comprises an array of first electrodes 11 which are formed in a stripe pattern, a dielectric layer 12 which is laminated on the array of the first electrodes 11 and in which a plurality of holes are arrayed, an array of the nanotubes 19 which have contact with the array of the first electrodes 11 and are vertically grown inside the holes in the dielectric layer 12 to emit electrons, an array of second electrodes 13 which have contact with the array of the nanotubes 19 and are formed in a stripe pattern on the dielectric layer 12 so as to be orthogonal to the first electrodes 11, memory cells 15 which are positioned on the array of the second electrodes 13 and capture the electrons emitted from the array of the nanotubes 19, and a gate electrode 17 which is laminated on the the memory cell 15 and forms an electric field in the periphery of the array of the nanotubes 19. COPYRIGHT: (C)2005,JPO&NCIPI
Bibliography:Application Number: JP20030401458