ALIGNER, ALIGNMENT METHOD, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To satisfactorily maintain the connecting accuracy between complementarily divided areas even when, for example, a shot rotation in substrate pattern occurs and, in addition, to suppress the deterioration of yield as much as possible at the time of forming a pattern through com...

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Bibliographic Details
Main Author NOUDO SHINICHIRO
Format Patent
LanguageEnglish
Published 30.04.2004
Edition7
Subjects
APPARATUS SPECIALLY ADAPTED THEREFOR
BASIC ELECTRIC ELEMENTS
CINEMATOGRAPHY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
ELECTROGRAPHY
HOLOGRAPHY
MATERIALS THEREFOR
ORIGINALS THEREFOR
PHOTOGRAPHY
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:PROBLEM TO BE SOLVED: To satisfactorily maintain the connecting accuracy between complementarily divided areas even when, for example, a shot rotation in substrate pattern occurs and, in addition, to suppress the deterioration of yield as much as possible at the time of forming a pattern through complementary division. SOLUTION: At the time of transferring a pattern by using a complementarily divided mask 4, alignment marks 3a and 3b are put on the scribed line 2 of a wafer 1 to be exposed and, at the same time, commonly used by adjacent original pattern regions in a shared state. In addition, the wafer 1 is aligned relatively to the mask 4 by optically detecting the alignment marks 3a and 3b and alignment marks 5a and 5b put on the mask 4. COPYRIGHT: (C)2004,JPO
Bibliography:Application Number: JP20020295670