PROGRAMMABLE LOGIC CIRCUIT AND COMPUTER SYSTEM, AND CACHE METHOD

PROBLEM TO BE SOLVED: To provide a programmable logic circuit and a computer system for utilizing limited hardware so as to process a variety of applications including multi-tasks at high speed and to provide a cache method. SOLUTION: The rewritable area of the programmable logic circuit is nearly e...

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Bibliographic Details
Main Authors YAMAMOTO NAOTO, KOMASAKA TOMONORI, NAKANO KUNIO, KOYANAGI HITOSHI
Format Patent
LanguageEnglish
Published 05.12.2003
Edition7
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
PULSE TECHNIQUE
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Summary:PROBLEM TO BE SOLVED: To provide a programmable logic circuit and a computer system for utilizing limited hardware so as to process a variety of applications including multi-tasks at high speed and to provide a cache method. SOLUTION: The rewritable area of the programmable logic circuit is nearly equally divided into individually accessible slots 10 and includes at input and output stages: a slot input control section 11 and a slot output control section 12 for arbitrating between external hardware and software and a hardware logic to be written to the plurality of slots 10; an interrupt control section 13 capable of realizing interrupt control of the hardware logic; and a status 14 exhibiting the status of each slot. The hardware logic managed by the software is written to each slot while the control sections arbitrate between the hardware and the software to allow the hardware to carry out the processing required during the execution of the software at high speed. COPYRIGHT: (C)2004,JPO
Bibliography:Application Number: JP20020153586