SEMICONDUCTOR MEMORY

• Main Author: KIKUKAWA HIROHITO
• Format: Patent
• Language: English
• Published: 16.05.2003
• Edition: 7
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

PROBLEM TO BE SOLVED: To prevent remarkable degradation of operation performance caused by occurrence of mismatching between internal timing generation and external specifications in rewriting operation for a memory cell and bit line pre-charge operation and occurrence of reduction of yield caused by variation or the like of a process, in DRAM internal non-synchronous operation. SOLUTION: Operation timing of a row decoder driving a word line and a sense amplifier detecting and amplifying a level of a bit line is generated by using a circuit for delay being equal to a bit line amplification delay. A replica bit line 17 which is formed simultaneously with a normal bit line in a memory cell array part 1, intersected with the same number of word lines as in the case of normal bit lines, and to which the same number of memory cells are connected is used as a load element of the delay circuit, and a replica sense amplifier 16 being similar to a normal sense amplifier is used as a driver driving the load element.