METHOD FOR REDUCING PARASITIC CAPACITANCE OF ELEMENT USING LOWER FACE CRYSTALLIZATION DIRECTION SELECTIVE ETCHING

• Main Authors: RYO KEIKUN, YOON MYOUNG HOON
• Format: Patent
• Language: English
• Published: 09.05.2003
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To manufacture an element which has reduced parasitic capacitance through a simple step, self alignment process realized, and stable structure. SOLUTION: An emitter metal layer 118 is vapor-deposited on an InGaAs emitter layer 116 laminated on the uppermost layer above an InP substrate 100, and the upper surface of an InGaAs base layer 110 is partly exposed by etching and a photo resist 120 is applied thereto, to protect the emitter region. Then, the exposed part of the InGaAs base layer 110 is etched for removal, and an InP collector layer 108 is etched using the remaining InGaAs base layer 110 as a mask, to partly expose the upper surface of a second InGaAs sub- collector layer 106 and selectively side-etch the sub-collector layer 106. Thus, since the lower surface of the InP collector layer 108 is partly exposed, upward crystallographically defined anisotropic selective etching is used to remove a part which contributes to parasitic capacitance.