SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREFOR

PROBLEM TO BE SOLVED: To eliminate chip placement failure due to the formation of burrs on the chip placement side of die pads of a lead frame. SOLUTION: In a semiconductor integrated circuit device wherein the size of the die pads of the lead frame 1 is larger than the size of a semiconductor chip,...

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Main Authors KAWAI SUEO, KAJIWARA YUJIRO, SUZUKI KAZUNARI, NAITO TAKAHIRO, SUZUKI HIROMICHI, TSUBOSAKI KUNIHIRO, MIYAKI YOSHINORI
Format Patent
LanguageEnglish
Published 15.11.2002
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PROBLEM TO BE SOLVED: To eliminate chip placement failure due to the formation of burrs on the chip placement side of die pads of a lead frame. SOLUTION: In a semiconductor integrated circuit device wherein the size of the die pads of the lead frame 1 is larger than the size of a semiconductor chip, the faces of the die pads on the side where burrs 11 are not formed during die pad forming operation are used as the chip placement faces of the die pads. The faces of the inner leads of the lead frame 1 on the side where burrs 11 are formed during inner lead forming operation are used as the bonding wire bonding faces of the inner leads.
Bibliography:Application Number: JP20020128665