BUS INTERFACE
PROBLEM TO BE SOLVED: To smoothly carry out data transfer even if the data transfer by a master operation and the data transfer by a target operation arise at the same time, when the data transfer is carried out between a CPU bus and a PCI bus. SOLUTION: When assigning a right to use a second bus 23...
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Main Author | |
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Format | Patent |
Language | English |
Published |
18.10.2002
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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Summary: | PROBLEM TO BE SOLVED: To smoothly carry out data transfer even if the data transfer by a master operation and the data transfer by a target operation arise at the same time, when the data transfer is carried out between a CPU bus and a PCI bus. SOLUTION: When assigning a right to use a second bus 23, data to transfer are formed into data groups having proper sizes. Every time transfer of one data group is finished, a second bus 23 is opened. If a demand for the data transfer by the second bus 23 by the master operation arises while carrying out the data transfer by the second bus 23 by the target operation, priority is given to the data transfer by the target operation. If a demand for the data transfer by the second bus 23 by the target operation arises while carrying out the data transfer by the second bus 23 by the master operation, the data transfer by the second bus 23 by the target operation is carried out after the data transfer of one data group by the second bus 23 by the master operation is finished. |
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Bibliography: | Application Number: JP20010105883 |