ARCHITECTURE FOR CIRCUIT CONNECTION OF VERTICAL TRANSISTOR

• Main Authors: II-FEN CHAN, MONROE DONALD P, JOHN MICHAEL HAGENROSER
• Format: Patent
• Language: English
• Published: 31.05.2002
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To provide structure for connecting regions in a semiconductor layer or adjacent to the semiconductor layer. SOLUTION: A device includes a first layer 100 and A first MOSFET 180 having first source/drain regions formed in the first layer 100. A channel region is formed on the first layer 100 and second source/drain regions 152 is formed on the channel region 160. The device includes a second MOSFET 190 having a first source/drain regions 154 formed on the first layer 100. The channel region 162 of the second MOSFET 190 is formed on the first layer 100 and the second source/drain regions 154 is formed on the channel region 162. A conductive layer 120 is placed between the first source/drain regions of the respective MOSFET and they introduce current to the first source/drain regions 14 from one first source/drain regions 152.