SEMICONDUCTOR MEMORY

PROBLEM TO BE SOLVED: To provide a semiconductor memory which permits high speed write-in cycle for a memory cell without requiring a standby time for shift decoding operation in accordance with a defective address is decided even if a data line shift system is used for relieving defect. SOLUTION: T...

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Bibliographic Details
Main Authors KAWASAKI TOSHIAKI, KIKUKAWA HIROHITO
Format Patent
LanguageEnglish
Published 26.04.2002
Edition7
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PROBLEM TO BE SOLVED: To provide a semiconductor memory which permits high speed write-in cycle for a memory cell without requiring a standby time for shift decoding operation in accordance with a defective address is decided even if a data line shift system is used for relieving defect. SOLUTION: This device is provided with a first internal clock generating circuit 6 generating a first internal clock Int-CLK1 in accordance with an inputted external clock Ext-CLK and a second internal clock generating circuit 7 generating a second internal clock Int-CLK2 having more lead phase than the first internal clock in accordance with an external clock, and decode-decision by a decoding circuit 4 based on a defective address signal FASS can be performed relatively more quickly than data-decision by taking an external data Ext-Ion in the inside based on the first internal clock in an input output buffer circuit 5 and taking an external column address Ext-CAD in the inside in a latch circuit 8.
Bibliography:Application Number: JP20000311989