CACHE CONTROLLER AND PROCESSOR

PROBLEM TO BE SOLVED: To shorten latency in the case of a cache miss by making a start in advance of a cache memory reference instruction and performing data replacement. SOLUTION: For cache replacement control over a load store unit, a 1st queue selection logic circuit 41, a 2nd queue selection log...

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Bibliographic Details
Main Author MUTA TOSHIYUKI
Format Patent
LanguageEnglish
Published 12.04.2002
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PROBLEM TO BE SOLVED: To shorten latency in the case of a cache miss by making a start in advance of a cache memory reference instruction and performing data replacement. SOLUTION: For cache replacement control over a load store unit, a 1st queue selection logic circuit 41, a 2nd queue selection logic circuit 42, and an arbitration part are provided, the 1st queue selection logic circuit sequentially select access instructions to a cache memory stored in a queue 31, the 2nd queue selection logic circuit selects unissued access instructions stored in the queue as to the access instructions to the cache memory in advance to the selection by the 1st queue selection logic circuit, and the arbitration part arbitrates the access instructions selected by the 1st queue selection logic circuit and the precedent access instructions selected by the 2nd queue selection logic circuit to access the cache memory.
Bibliography:Application Number: JP20000302795