MULTI-LEVEL MEMORY

PROBLEM TO BE SOLVED: To provide a multi-level memory realizing the improvement of write-in operation margin and yield of products while narrowing the distribution of threshold voltage corresponding to multi-level information. SOLUTION: In a multi-level memory provided with memory cells of a two lay...

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Bibliographic Details
Main Authors NOZOE ATSUSHI, KISHIMOTO JIRO
Format Patent
LanguageEnglish
Published 11.01.2002
Edition7
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PROBLEM TO BE SOLVED: To provide a multi-level memory realizing the improvement of write-in operation margin and yield of products while narrowing the distribution of threshold voltage corresponding to multi-level information. SOLUTION: In a multi-level memory provided with memory cells of a two layer gate structure type distributed so that threshold voltage after erasion is a target value of the first threshold voltage and threshold voltage after write-in is a target value of the second to (p)th threshold voltage, when defect is detected by disturbance corresponding to the (p-1)th threshold voltage after write-in operation for a memory cell in which a target value of the threshold voltage is to be the second to (p-1)th threshold voltage, write-in quantity per one time for a memory cell to be the second to the (p-1)th threshold voltage is made smaller than that of the previous time in rewriting after a memory cell is put into an erasion state in which the first threshold voltage is a target value.
Bibliography:Application Number: JP20000186617