CLOCK GENERATION DEVICE, BUS INTERFACE CONTROLLER AND INFORMATION PROCESSOR

PROBLEM TO BE SOLVED: To mount plural clock systems with respect to an inner clock and an outer unit only by the distribution system of an inner clock one system and to control frequency conversion only by a logic circuit. SOLUTION: A processor system 21 has a means 25 for generating a reference syn...

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Bibliographic Details
Main Authors YAMATO AKIHIRO, YAMAMOTO TAKASHI, YAMAGATA MAKOTO, SHIMODA TERUAKI
Format Patent
LanguageEnglish
Published 28.09.2001
Edition7
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
PULSE TECHNIQUE
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Summary:PROBLEM TO BE SOLVED: To mount plural clock systems with respect to an inner clock and an outer unit only by the distribution system of an inner clock one system and to control frequency conversion only by a logic circuit. SOLUTION: A processor system 21 has a means 25 for generating a reference synchronizing signal for synchronization in the pertinent device from a reference clock for synchronization with peripheral equipment and generating an inner operation clock. The means generates the inner clock by changing the duty of respective clock cycles. A bus access timing signal generation circuit 24 sets the reference synchronizing signal as a reset signal, has a synchronous counter deciding the number of counts by a frequency ratio which is previously set and generates the access timing signal with peripheral equipment. A bus input/output signal conversion circuit 23 synchronously accesses plural processors having clock systems operating at plural different speeds such as an outer bus by setting the access timing signal as the enable signal of the enable latch of an outer interface.
Bibliography:Application Number: JP20000080738