CHIP-TYPE LAMINATED VARISTOR

PROBLEM TO BE SOLVED: To provide a chip-type laminated varistor which is mainly composed of SrTiO3 and protected against cracking at soldering. SOLUTION: A ceramic layer 3 mainly composed of calcined SrTiO3 of grain diameter 0.6 to 0.7 μm and inner electrodes layers 4 and 5 whose main components are...

Full description

Saved in:
Bibliographic Details
Main Author AMISAWA MIKINORI
Format Patent
LanguageEnglish
Published 28.09.2001
Edition7
Subjects
ARTIFICIAL STONE
BASIC ELECTRIC ELEMENTS
CEMENTS
CERAMICS
CHEMISTRY
COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDINGMATERIALS
CONCRETE
ELECTRICITY
LIME, MAGNESIA
METALLURGY
REFRACTORIES
RESISTORS
SLAG
TREATMENT OF NATURAL STONE
Online AccessGet full text

Cover

More Information
Summary:PROBLEM TO BE SOLVED: To provide a chip-type laminated varistor which is mainly composed of SrTiO3 and protected against cracking at soldering. SOLUTION: A ceramic layer 3 mainly composed of calcined SrTiO3 of grain diameter 0.6 to 0.7 μm and inner electrodes layers 4 and 5 whose main components are NiO are alternately laminated into a laminate, and the laminate is baked into a sintered body 2, and outer electrodes are provided to the sintered body 2 for the formation of a chip-type laminated varistor 1, where the above NiO particles have such a grain diameter distribution that 10% average grain diameter (D10) is 0.40 to 0.45 μm, 50% average grain diameter (D50) is 0.70 to 0.80 μm, and 90% average grain diameter (D90) is 1.50 to 1.65 μm.
Bibliography:Application Number: JP20000076205