BUS SYSTEM FOR INFORMATION PROCESSOR

PROBLEM TO BE SOLVED: To provide a bus system for information processor for maximizing the using efficiency of the three kinds of buses that are system bus, a memory bus and a processor bus. SOLUTION: The processor bus 111 connected to a processor 101, the memory bus 112 connected to a main memory 1...

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Bibliographic Details
Main Authors MOCHIDA TETSUYA, KAWAGUCHI HITOSHI, KOBAYASHI ICHIJI, KIMURA KOICHI, OKAZAWA KOICHI, YUNO KAZUHARU
Format Patent
LanguageEnglish
Published 10.08.2001
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PROBLEM TO BE SOLVED: To provide a bus system for information processor for maximizing the using efficiency of the three kinds of buses that are system bus, a memory bus and a processor bus. SOLUTION: The processor bus 111 connected to a processor 101, the memory bus 112 connected to a main memory 104 and the system bus 113 connected to an input/output device 105 are connected to a three-forked path connection control means 103. The three-forked path connection control means 103 is provided with a data switch connected to the respective address buses, control buses and data buses of the processor bus 111, the memory bus 112 and the system bus 113 for mutually transferring address and control signal and mutually transferring data on the data buses in accordance with data bus control signal.
Bibliography:Application Number: JP20000377988